VLSI DESIGN STYLES

  The electronics industry has developed at a breakneck pace over the last two decades, owing primarily to rapid advancements in integration technologies and large-scale systems design - in other words, the introduction of VLSI. The number of integrated circuit applications in high-performance computing, telecommunications, and consumer electronics has been steadily increasing at a rapid rate.The requisite computational power (or, in other words, intelligence) of these applications is typically the driving force behind the field's rapid growth. The need to incorporate these functions in a small system/package is growing as more complex functions are needed in various data processing and telecommunications devices. For almost three decades, the degree of integration, as calculated by the number of logic gates in a monolithic chip, has been steadily increasing, owing to rapid advances in processing and interconnect technology.The given figure shows the evolution of logic complexity...

 Very-large scale integration (VLSI) is the process of incorporating thousands of transistors into a single chip to create an integrated circuit (IC) . VLSI got its start in the 1970s, when complex semiconductor and communication technologies were being developed.   The  microprocessor  is a VLSI device. A limited set of functions were performed by most ICs prior to the introduction of VLSI technology. An electronic circuit contains a CPU, ROM, RAM, etc. IC designers can integrate all of these functions into a single chip using VLSI. Thanks to rapid advancements in large-scale integration technologies and device design applications, the electronics industry has grown at a breakneck rate in recent decades.Since the introduction of very large scale integration (VLSI) designs, the number of integrated circuits (ICs) used in high-performance computing, controllers, telecommunications, image and video processing, and consumer electronics has been increasingly growing...

                                        Figure-:  A  simplified view of VLSI design flow. Figure  depicts the VLSI design flow in a more condensed manner, taking into account the various design representations, or abstractions  such as design- behavioural, logic, circuit, and mask layout. It's worth noting that concept verification is crucial at any stage of this procedure.Failure to properly verify a design in its early stages often results in substantial and costly re-design at a later level, increasing time-to-market. Although the design process has been represented in a linear fashion for ease of understanding, there are several iterations back and forth in practise, particularly between any two neighbouring steps, and sometimes even between pairs of steps that are far apart. Although top-down design flow is effective at controlling the design process, there i...

  The hierarchy, or 'divide and conquer' strategy, entails breaking down a subsystem into sub-modules and then repeating the process on the sub-modules until the smaller parts' complexity is manageable. This method is similar to how large programmes are broken down into smaller and smaller parts before simple subroutines with well-defined functions and interfaces can be written in software.  It is nothing but dividing the task into smaller tasks until it reaches to its simplest level. This process is most suitable because the last evolution of design has become so simple that its manufacturing becomes easier. We can design the given task into the design flow process's domain (Behavioral, Structural, and Geometrical). To understand this, let’s take an example of designing a 16-bit adder, as shown in the figure below. Here, the whole chip of 16 bit adder is divided into four modules of 4-bit adders. Further, dividing the 4-bit adder into 1-bit adder or half adder. 1 bit a...

        By splitting the large structure into many sub-modules, the hierarchical design approach eliminates design complexity. To make the process easier, other design principles and approaches are usually needed. Regularity ensures that a large system's hierarchical decomposition can produce as many simple and identical blocks as possible.The design of array structures made up of similar cells, such as a parallel multiplication array, is a good example of regularity. Regularity can be seen at all levels of abstraction: uniformly sized transistors simplify the design at the transistor stage. Identical gate structures can be used at the logic level, and so on.      The different functional blocks that make up the larger structure must have well-defined functions and interfaces, which is referred to as modularity in design. Since there is no doubt about the purpose and signal interface of these blocks, modularity allows each block or module to be co...

  For chip implementation of specified algorithms or logic functions, a variety of design styles can be considered. Each design style has its own advantages and disadvantages, so designers must make an informed decision in order to provide functionality at a low cost. Field Programmable Gate Array (FPGA) The full form of  FPGA  is “ Field Programmable Gate Array ”. It  s made up of tens of thousands to millions of  logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily. A typical model FPGA chip is shown in the given figure. There are I/O blocks, which are designed and numbered according to function. For each module of logic level composition, there are  CLB’s (Configurable Logic Blocks) .      CLB executes the logic operation that the module has been provided. The inter connection between CLB and I/O blocks are made with the help of horizontal routin...

In terms of quick prototyping capacity, the gate array (GA) comes in second after the FPGA. Metal mask design and processing are used for GA, while user programming is essential for the FPGA chip's design implementation. A two-step manufacturing process is needed for gate array implementation. On each GA chip, the first phase results in an array of uncommitted transistors. These uncommitted chips can be stored for later customization after the metal interconnects between the array's transistors are defined. The patterning of metallic interconnects occurs at the end of the chip fabrication process, allowing for a relatively quick turnaround period of a few days to a few weeks. Typical gate array platforms use dedicated areas called channels, for inter-cell routing between rows or columns of MOS transistors. They simplify the interconnections. Interconnection patterns that perform basic logic gates are stored in a library, which can then be used to customize rows of uncommitted ...

A standard cell based design needs development of a full custom mask set. The standard cell is additionally referred to as the polycell. In this approach, all of the commonly used logic cells are developed, characterized and stored during a galvanic cell library. A library may contain a couple of hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches and Flip-flops. Each gate type are often implemented in several versions to supply adequate driving capability for various fan-outs. The inverter gate can have standard size, double size, and quadruple size so as that the chip designer can select the proper size to urge high circuit speed and layout density. Each cell is characterized consistent with several different characterization categories, such as, • Delay time versus load capacitance • Circuit simulation model • Timing simulation model • Fault simulation model • Cell data for place-and-route • Mask data For automated placement of the cells and r...

 While the standard-cells-based design is often referred to as full custom design , it is less so in a strict sense because the cells are pre-designed for general use and the same cells are used in a variety of chip designs. In a more comprehensive custom design, the whole mask is created from scratch, without the use of any libraries.However, the expense of developing a design style like this is becoming prohibitively expensive. As a result, the idea of design reuse is gaining attention and becoming popular  as a way to cut down on design cycle time and production costs. The design of a memory cell, whether static or dynamic, may be the most rigorous complete custom design.There will be no alternative to high density memory chip design , since the same layout design  is repeated.Using a combination of different design types on the same chip, such as regular cells, data-path cells, and PLAs, can achieve a good compromise in logic chip design. Design productivity is normal...

  Testing and design verification  IIt is worthless , if a fabricated device cannot be tested.However, with many modern VLSI designs, particularly those with large amounts of RAM, complete testing is nearly impossible. A agreement must be achieved in which the test technique used demonstrates that the design is likely right. Designing for testability is a subject in and of itself, and it is discussed elsewhere. Verification of full custom designs is necessary to prevent the designer from making an error when converting from the desired schematic to layout type. The danger (in terms of wasted time and fabrication costs) necessitates making every effort to ensure that the schematic and layout correspond to identical circuits. Verification involves extracting  a netlist and a list of components  from the physical layout. The netlist can then be compared with the original schematic. Checkers for open circuits or shorts in the power distribution system, as well as inadver...