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Gate Array Design

In terms of quick prototyping capacity, the gate array (GA) comes in second after the FPGA. Metal mask design and processing are used
for GA, while user programming is essential for the FPGA chip's design implementation. A two-step manufacturing process is needed for gate array implementation.

On each GA chip, the first phase results in an array of uncommitted transistors. These uncommitted chips can be stored for later customization after the metal interconnects between the array's transistors are defined. The patterning of metallic interconnects occurs at the end of the chip fabrication process, allowing for a relatively quick turnaround period of a few days to a few weeks.


Typical gate array platforms use dedicated areas called channels, for inter-cell routing between rows or columns of MOS transistors. They simplify the interconnections. Interconnection patterns that perform basic logic gates are stored in a library, which can then be used to customize rows of uncommitted transistors according to the netlist.

In most of the modern GAs, multiple metal layers are used for channel routing. With the use of multiple interconnected layers, the routing can be achieved over the active cell areas; so that the routing channels can be removed as in Sea-of-Gates (SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and pMOS transistors. The neighboring transistors can be customized using a metal mask to form basic logic gates.

For inter cell routing, some of the uncommitted transistors must be sacrificed. This design style results in more flexibility for interconnections and usually in a higher density. GA chip utilization factor is measured by the used chip area divided by the total chip area. It is higher than that of the FPGA and so is the chip speed.



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