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Comparison Among Various Design Styles

 Testing and design verification

 IIt is worthless , if a fabricated device cannot be tested.However, with many modern VLSI designs, particularly those with large amounts of RAM, complete testing is nearly impossible. A agreement must be achieved in which the test technique used demonstrates that the design is likely right. Designing for testability is a subject in and of itself, and it is discussed elsewhere.

Verification of full custom designs is necessary to prevent the designer from making an error when converting from the desired schematic to layout type.

The danger (in terms of wasted time and fabrication costs) necessitates making every effort to ensure that the schematic and layout correspond to identical circuits.

Verification involves extracting  a netlist and a list of components  from the physical layout. The netlist can then be compared with the original schematic.

Checkers for open circuits or shorts in the power distribution system, as well as inadvertent shorting of gate outputs, are available.

Extractors can deduce details about the components that make up a physical design (for example, capacitance and resitance values, transistor dimensions, and occasionally inductance values). To check for mistakes, these are often compared to the schematic.

Timing verification requires accurate models of the circuit elements and a suitable means for precise definition of rise and fall times. This is reasonably practical where the number of active devices is not too great by use of circuit simulators. Where thousands of gates are present, such simulators cannot be used, and logic simulators with simpler and less accurate  and precise device models must be used.

Comparison Among Various Design Styles





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