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Standard-Cells Based Design

A standard cell based design needs development of a full custom mask set. The standard cell is additionally referred to as the polycell. In this approach, all of the commonly used logic cells are developed, characterized and stored during a galvanic cell library.

A library may contain a couple of hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches and Flip-flops. Each gate type are often implemented in several versions to supply adequate driving capability for various fan-outs. The inverter gate can have standard size, double size, and quadruple size so as that the chip designer can select the proper size to urge high circuit speed and layout density.

Each cell is characterized consistent with several different characterization categories, such as,

• Delay time versus load capacitance

• Circuit simulation model

• Timing simulation model

• Fault simulation model

• Cell data for place-and-route

• Mask data

For automated placement of the cells and routing, each cell layout is meant with a hard and fast height, in order that variety of cells are often bounded side-by-side to make rows. The power and ground rails run parallel to upper and lower boundaries of cell. So that, neighbouring cells share a standard power bus and a standard ground bus. The figure shown below may be a floorplan for standard-cell based design.


 









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